1. Field of the Invention
The field of the invention is memory systems for automated computing machinery.
2. Description of Related Art
The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
Contemporary high performance computing main memory systems incorporate memory devices in the array of dynamic random access memory (‘DRAM’) devices. FIG. 1 illustrates an example of a prior art memory system that includes a memory controller (102), memory modules (124), memory buffer devices (128), and memory devices (125, 126, 127) organized in a hub-and-spoke topology, with the memory buffer devices as ‘hubs’ and memory devices representing ‘spokes.’ The memory controller (102) is interconnected to memory buffer devices (128) via one or more physical high speed, unidirectional links that include outbound links (116, 108, 112) and inbound links (120, 109, 113). Each memory buffer device provides one or more lower speed independent connections to banks of memory devices (125, 126, 127). An example of such a prior art memory system architecture is described in the Jedec standard for the so-called ‘Fully Buffered Dual Inline Memory Module,’ or ‘FBDIMM.’ The example of FIG. 1 illustrates only one ‘channel’ or network of memory buffer devices and links among memory buffer devices and memory controllers. Practical memory systems, however, typically may be implemented with a number of such channels or networks. Each such channel may include memory modules logically grouped together in ranks (125, 126, 127) operated in unison by the memory controller for optimal latency, bandwidth, and error correction effectiveness for system memory cache line transfer (typically 64 bytes or 128 bytes).
The memory controller (102) translates system requests from system processor (156) for memory access into packets according to the memory system network communication protocol. A memory ‘write’ packet of such a protocol may include a command (‘read’ or ‘write’), and address, and associated data, and a memory ‘read’ packet may include a command and address. Memory read packets imply an expected packet will be returned to the memory controller containing data read from memory.
Memory access latency in memory system network topologies composed of cascaded memory buffer devices together with point-to-point electrical or optical links is degraded by having to propagate through each memory buffer device in a cascaded network of memory buffer devices between a particular rank of memory devices and a memory controller. For purposes of explanation, the transition delay for signal transition across a memory buffer device may be taken as one unit of latency. The latency for transmission of memory signals between memory controller (102) and memory devices in rank 1 (125) therefore may be said to have a value of 1. The latency for transmission of memory signals between memory controller (102) and memory devices in rank 2 (126) has a value of 2. And so on, so that the latency for transmission of memory signals between memory controller (102) and memory devices in any rank X (127) is taken as the value X.
In addition to issues with memory access latency, power consumption and cost for interfaces is maximized by having point-to-point network connections. In the memory system of FIG. 1, for example, the memory controller and each memory buffer device drives output memory signals across the full width of each link. If there are 10 lines in an outbound link, the memory controller or memory buffer device driving the link has 10 output drivers in its output interface to the link with a power requirement to supply all 10 drivers. For all these reasons, there is an ongoing need for innovation in the field of memory systems.